ISSUE: What is Dual Channel memory?
Dual-channel memory doubles the amount of data sent from RAM to the memory controller, enabling two 64-bit data channels to equal 128 bits of bandwidth.
Immediately prior to Dual DDR in desktop motherboards, Intel Northbridge chipsets (containing the memory controller and memory controller hub) used a 64-bit wide memory bus, which meant that every data transfer between the memory controller and the memory would result in 64 bits of data moving from one to the other. The speed and data width resulted in bandwidths of 3.2GBs (GigaBytes) for PC3200 (DDR400) and 2.7GBs for PC2700 (DDR333). The speed of the memory bus became a major limiting factor for the memory bus bandwidth. While this bandwidth is much faster compared to SDRAM bandwidth (PC133 has a bandwidth of 1.066GBs), it limits the amount of data transfer between the Northbridge and the processor (FSB – Front Side Bus connects the two), which operates at a greater speed and bandwidth. Limited data transfer causes latency periods, or wait states, where the processor is idle while waiting for data.
With the introduction of the 875 and 865 chipsets, Intel added a second 64-bit wide memory bus between the memory and the memory controller, which allows a transfer of 128 bits of data each time an address in the memory is accessed. With PC3200, bandwidth doubles from 3.2GBs to 6.4GBs. Using a FSB speed of 800MHz, FSB bandwidth is also 6.4GBs. When the two bus bandwidths match, the processor doesn’t go hungry, waiting for data to crunch.
For the memory to function in Dual DDR mode, DDR modules must be installed in matched pairs. A common misconception is that “matched pairs” mean the modules must be tested as a pair by the manufacturer. A matched pair simply means the modules are built with the same architecture of RAM chips (i.e. 32x8 or 16x8 chips), are the same speed, and are the same size (MBs – MegaBytes). Matched pairs allow the memory controller to address both modules with the same addressing scheme simultaneously. When unmatched pairs are installed, the memory controller functions in Single DDR mode, effectively reducing the memory bus to 64